MOSEL VITELIC
V53C516405A
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C516405A
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
50
50 ns
25 ns
20 ns
84 ns
60
60 ns
30 ns
25 ns
104 ns
Features
s
4M x 4-bit organization
s
EDO Page Mode for a sustained data rate
of 50 MHz
s
RAS access time: 50, 60, 70 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
s
Single +5 V
±
10% Power Supply
s
TTL Interface
Description
The V53C516405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access
memory. The V53C516405A offers Page mode
operation with Extended Data Output. The
V53C516405A has a symmetric address, 12-bit row
and 10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C516405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
K
•
Access Time (ns)
50
•
Power
Std.
•
T
•
60
•
Temperature
Mark
Blank
V53C516405A Rev. 1.1 March 1998
1
MOSEL VITELIC
24/26 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
WE
RAS
A
11
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
511740502-02
V53C516405A
Pin Names
A
0
–A
11
RAS
Row, Column Address Inputs
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Data Input, Output
+5V Supply
0V Supply
No Connect
V
SS
I/O
4
I/O
3
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CAS
WE
OE
I/O
1
–I/O
4
V
CC
V
SS
NC
Description
SOJ
TSOP-II
Pkg.
K
T
Pin Count
24/26
24/26
V53C516405A Rev. 1.1 March 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
°
C
Storage temperature range ............... -55 to 150
°
C
Input/output voltage ....... -0.5 to min (V
CC
+0.5, 7) V
Power supply voltage ............................-1.0V to 7V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
V53C516405A
Capacitance*
Symbol
C
IN1
C
IN2
C
OUT
T
A
= 25
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, f = 1 MHz
Parameter
Address Input
RAS, CAS, WE, OE
Data Input/Output
Min.
—
—
—
Max.
5
7
7
Unit
pF
pF
pF
*Note:
Capacitance is sampled and not 100% tested.
Block Diagram
4096 x 4
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
WE
CAS
4
Data Out
Buffer
4
OE
No. 2 Clock
Generator
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Column
Address
Buffers (10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (12)
12
12
Row
Address
Buffers (12)
12
Row
Decoder 4096
Memory Array
4096 x 1024 x 4
1024
x4
4
RAS
No. 1 Clock
Generator
Voltage Down
Generator
VCC
511640502-03
VCC (internal)
V53C516405A Rev. 1.1 March 1998
3
MOSEL VITELIC
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Access
Time
V53C516405A
Min.
–10
V53C516405A
DC and Operating Characteristics
(1-2)
Symbol
I
LI
I
LO
I
CC1
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
V
CC
Supply Current,
Operating
V
CC
Supply Current,
TTL Standby
V
CC
Supply Current,
RAS-Only Refresh
V
CC
Supply Current,
EDO Page Mode
Operation
V
CC
Supply Current,
during CAS-before-RAS
Refresh
V
CC
Supply Current,
CMOS Standby
Typ.
Max.
10
Unit
µ
A
µ
A
mA
Test Conditions
V
SS
≤
V
IN
≤
V
CC
+ 0.5V
V
SS
≤
V
OUT
≤
V
CC
+ 0.5V
RAS, CAS at V
IH
t
RC
= t
RC
(min.)
Notes
1
–10
10
1
50
60
80
70
2
2, 3, 4
I
CC2
I
CC3
mA
RAS, CAS at V
IH
other inputs
≥
V
SS
t
RC
= t
RC
(min.)
2, 4
50
60
50
60
50
60
80
70
35
30
120
110
1.0
mA
I
CC4
mA
Minimum Cycle
2, 3, 4
I
CC5
mA
2, 4
I
CC6
mA
RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V
other inputs
≥
V
SS
1
V
CC
V
IL
V
IH
V
OL
V
OH
Power Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
4.5
–0.5
2.4
5.0
5.5
0.8
V
V
1
1
I
OL
= 4.2 mA
I
OH
= –5 mA
1
1
V
CC
+0.5 V
0.4
V
V
2.4
V53C516405A Rev. 1.1 March 1998
4
MOSEL VITELIC
AC Characteristics
(5, 6)
T
A
= 0 to 70 ˚C,V
CC
= 5 V
±
10 %, t
T
= 2 ns
-50
#
Symbol
Parameter
min.
max.
min.
-60
V53C516405A
max.
Unit
Note
Common Parameters
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
84
30
50
8
0
8
0
8
12
10
13
40
5
1
–
–
50
64
–
–
10k
10k
–
–
–
–
37
25
104
40
60
10
0
10
0
10
14
12
15
50
5
1
–
–
–
10k
10k
–
–
–
–
45
30
–
–
–
50
64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
7
Read Cycle
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
t
RAC
t
CAC
t
CAA
t
OEA
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF
t
OEZ
t
DZC
t
DZO
t
CDD
t
ODD
Access time from RAS
Access time from CAS
Access time from column address
OE access time
Column address to RAS lead time
Read command setup time
Read command hold time
Read command hold time referenced to RAS
CAS to output in low-Z
Output buffer turn-off delay
Output turn-off delay from OE
Data to CAS low delay
Data to OE low delay
CAS high to data delay
OE high to data delay
–
–
–
–
25
0
0
0
0
0
0
0
0
10
10
50
13
25
13
–
–
–
–
–
13
13
–
–
–
–
–
–
–
–
30
0
0
0
0
0
0
0
0
13
13
60
15
30
15
–
–
–
–
–
15
15
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
8
12
12
13
13
14
14
8, 9
8, 9
8,10
V53C516405A Rev. 1.1 March 1998
5
嵌入式系统
